View IS61NVP102436-166TQI_3794514.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

integrated silicon solution, inc. 1 rev. 00a 05/02/07 is61nlp102436/is61nvp102436 is61nlp204818/is61nvp204818 copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtai n the latest version of this device specification before relying on any published information and before placing orders for products. features ? 100 percent bus utilization ? no wait cycles between read and write ? internal self-timed write cycle ? individual byte write control ? single r/w (read/write) control pin ? clock controlled, registered address, data and control ? interleaved or linear burst sequence control using mode input ? three chip enables for simple depth expansion and address pipelining ? power down mode ? common data inputs and data outputs ? cke pin to enable clock and suspend operation ? jedec 100-pin tqfp and 165-ball pbga packages ? power supply: nvp: v dd 2.5v ( 5%), v ddq 2.5v ( 5%) nlp: v dd 3.3v ( 5%), v ddq 3.3v/2.5v ( 5%) ? industrial temperature available ? lead-free available description the 36 meg 'nlp/nvp' product family feature high-speed, low-power synchronous static rams designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. they are organized as 1m words by 36 bits and 2m words by 18 bits, fabricated with issi 's advanced cmos technology. incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. this device integrates a 2-bit burst counter, high-speed sram core, and high-drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. operations may be suspended and all synchronous inputs ignored when clock enable, cke is high. in this state the internal device will hold their previous values. all read, write and deselect cycles are initiated by the adv input. when the adv is high the internal burst counter is incremented. new external addresses can be loaded when adv is low. write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when we is low. separate byte enables allow individual bytes to be written. a burst mode pin (mode) defines the order of the burst sequence. when tied high, the interleaved burst sequence is selected. when tied low, the linear burst sequence is selected. 1mb x 36 and 2mb x 18 36mb, pipeline 'no wait' state bus sram preliminary information june 2007 fast access time symbol parameter -200 -166 units t kq clock access time 3.1 3.5 ns t kc cycle time 5 6 ns frequency 200 166 mhz
2 integrated silicon solution, inc. ? www.issi.com rev. 00a 05/02/07 is61nlp102436/is61nvp102436 is61nlp204818/is61nvp204818 block diagram adv we } bw ? x (x=a,b,c,d or a,b) ce ce2 ce2 control logic 1mx36; 2mx18 memory array write address register write address register control logic output register buffer address register x 36: a [0:19] or x 18: a [0:20] clk cke a2-a19 or a2-a20 a0-a1 a'0-a'1 burst address counter mode data-in register data-in register control register oe zz 36 or 18 k k dqx/dqpx k k
integrated silicon solution, inc. ? www.issi.com 3 rev. 00a 05/02/07 is61nlp102436/is61nvp102436 is61nlp204818/is61nvp204818 pin configuration ? 1m x 36, 165-ball pbga (top view) 1234567891011 anc a ce bw c bw b ce 2 cke adv a a nc b nc a ce2 bw d bw a clk we oe aanc c dqpc nc v ddq v ss v ss v ss v ss v ss v ddq nc dqpb d dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb e dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb f dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb g dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb hnc nc nc v dd v ss v ss v ss v dd nc nc zz j dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa k dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa l dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa m dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa ndqpd nc v ddq v ss nc nc nc v ss v ddq nc dqpa pncnca anca1*nca a anc r mode a a a nc a0* nc a a a a note: a0 and a1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired . pin descriptions symbol pin name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance/ load we synchronous read/write control input clk synchronous clock cke clock enable ce , ce2 , ce2 synchronous chip enable bw x (x=a-d) synchronous byte write inputs oe output enable zz power sleep mode mode burst sequence selection v dd 3.3v/2.5v power supply nc no connect dqx data inputs/outputs dqpx parity data i/o v ddq isolated output power supply 3.3v/2.5v v ss ground
4 integrated silicon solution, inc. ? www.issi.com rev. 00a 05/02/07 is61nlp102436/is61nvp102436 is61nlp204818/is61nvp204818 165-pin pbga package configuration 2m x 18 (top view) pin descriptions symbol pin name a address inputs a0, a1 synchronous burst address inputs adv synchronous burst address advance/ load we synchronous read/write control input clk synchronous clock cke clock enable ce , ce2 , ce2 synchronous chip enable bw x (x=a,b) synchronous byte write inputs oe output enable zz power sleep mode 1234567891011 a a bw b cke bnc a we oe cnc nc vss vss dnc dqb vss vss nc enc dqb vss vss vss f nc dqb nc gnc dqb nc nc hnc nc v ddq j dqb nc dqa k dqb nc l dqb nc vss m dqb nc vss n dqpb nc vss vss nc pnc nc a 1 *nc r mode a nc ce2 vss vss vss vss vss vss vss vss nc a a a a a a a a a a a a a a a a ce v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq nc nc v dd v dd v dd v dd v dd v dd v dd v dd v dd nc bw a vss vss vss vss vss vss vss vss nc nc nc ce 2 clk vss nc a 0 * nc vss vss vss vss vss vss adv v dd v dd v dd v dd v dd v dd v dd v dd v dd v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq nc nc nc dqa dqa dqa nc nc nc nc nc nc nc zz dqa dqa dqa dqa dqpa note: a0 and a1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired . mode bu rst sequence selection v dd 3.3v/2.5v power supply nc no connect dqx data inputs/outputs dqpx parity data i/o v ddq isolated output power supply 3.3v/2.5v v ss ground
integrated silicon solution, inc. ? www.issi.com 5 rev. 00a 05/02/07 is61nlp102436/is61nvp102436 is61nlp204818/is61nvp204818 pin configuration 100-pin tqfp 2m x 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 a nc nc v ddq vss nc dqp a dqa dqa vss v ddq dqa dqa vss nc v dd zz dqa dqa v ddq vss dqa dqa nc nc vss v ddq nc nc nc nc nc nc v ddq vss nc nc dqb dqb vss v ddq dqb dqb vdd v dd nc vss dqb dqb v ddq vss dqb dqb dqpb nc vss v ddq nc nc nc a a ce ce2 nc nc bw b bw a ce2 v dd vss clk we cke oe adv a a a a m ode a a a a a1 a0 nc nc vss v dd nc a a a a a a a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 dqp b dqb dqb v ddq vss dqb dqb dqb dqb vss v ddq dqb dqb vss nc v dd zz dqa dqa v ddq vss dqa dqa dqa dqa vss v ddq dqa dqa dqp a dqpc dqc dqc v ddq vss dqc dqc dqc dqc vss v ddq dqc dqc vdd v dd nc vss dqd dqd v ddq vss dqd dqd dqd dqd vss v ddq dqd dqd dqpd a a ce ce2 bwd bwc bwb bwa ce2 v dd vss clk we cke oe adv a a a a m ode a a a a a1 a0 nc nc vss v dd nc a a a a a a a a 1m x 36 pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a synchronous address inputs clk synchronous clock adv synchronous burst address advance bw a- bw d synchronous byte write enable we write enable cke clock enable vss ground for core nc not connected ce , ce2, ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output dqpa-dqpd parity data i/o mode burst sequence selection v dd +3.3v/2.5v power supply v ss ground for output buffer v ddq isolated output buffer supply: +3.3v/2.5v zz snooze enable
6 integrated silicon solution, inc. ? www.issi.com rev. 00a 05/02/07 is61nlp102436/is61nvp102436 is61nlp204818/is61nvp204818 synchronous truth table (1) address operation used ce ce ce ce ce ce2 ce ce ce ce ce 2 adv we we we we we bw bw bw bw bw x oe oe oe oe oe cke cke cke cke cke clk not selected n/a h x x l x x x l not selected n/a x l x l x x x l not selected n/a x x h l x x x l not selected continue n/a x x x h x x x l begin burst read external address l h l l h x l l continue burst read next address x x x h x x l l nop/dummy read external address l h l l h x h l dummy read next address x x x h x x h l begin burst write external address l h l l l l x l continue burst write next address x x x h x l x l nop/write abort n/a l h l l l h x l write abort next address x x x h x h x l ignore clock current address x x x x x x x h notes: 1. "x" means don't care. 2. the rising edge of clock is symbolized by 3. a continue deselect cycle can only be entered if a deselect cycle is executed first. 4. we = l means write operation in write truth table. we = h means read operation in write truth table. 5. operation finally depends on status of asynchronous pins (zz and oe ). burst read deselect burst write begin read begin write read write read write burst burst burst ds ds ds read ds ds read write write burst burst write read state diagram
integrated silicon solution, inc. ? www.issi.com 7 rev. 00a 05/02/07 is61nlp102436/is61nvp102436 is61nlp204818/is61nvp204818 asynchronous truth table (1) operation zz oe oe oe oe oe i/o status sleep mode h x high-z read ll dq l h high-z write l x din, high-z deselected l x high-z notes: 1. x means "don't care". 2. for write cycles following read cycles, the output buffers must be disabled with oe , otherwise data bus contention will occur. 3. sleep mode means power sleep mode where stand-by current does not depend on cycle time. 4. deselected means power sleep mode where stand-by current depends on cycle time. write truth table (x18) operation we we we we we bw bw bw bw bw a bw bw bw bw bw b read h x x write byte a l l h write byte b l h l write all bytes l l l write abort/nop l h h notes: 1. x means "don't care". 2. all inputs in this table must beet setup and hold time around the rising edge of clk. write truth table (x36) operation we we we we we bw bw bw bw bw a bw bw bw bw bw b bw bw bw bw bw c bw bw bw bw bw d read h x x x x write byte a l l h h h write byte b l h l h h write byte c l h h l h write byte d l h h h l write all bytes l l l l l write abort/nop l h h h h notes : 1. x means "don't care". 2. all inputs in this table must beet setup and hold time around the rising edge of clk. interleaved burst address table (mode = v dd or nc) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00
8 integrated silicon solution, inc. ? www.issi.com rev. 00a 05/02/07 is61nlp102436/is61nvp102436 is61nlp204818/is61nvp204818 linear burst address table (mode = v ss ) absolute maximum ratings (1) symbol parameter value unit t stg storage temperature ?65 to +150 c p d power dissipation 1.6 w i out output current (per i/o) 100 ma v in , v out voltage relative to v ss for i/o pins ?0.5 to v ddq + 0.3 v v in voltage relative to v ss for ?0.3 to 4.6 v for address and control inputs notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up. 0,0 1,0 0,1 a1', a0' = 1,1 operating range (is61nlpx) range ambient temperature v dd v ddq commercial 0c to +70c 3.3v 5% 3.3v / 2.5v 5% industrial -40c to +85c 3.3v 5% 3.3v / 2.5v 5% operating range (is61nvpx) range ambient temperature v dd v ddq commercial 0c to +70c 2.5v 5% 2.5v 5% industrial -40c to +85c 2.5v 5% 2.5v 5%
integrated silicon solution, inc. ? www.issi.com 9 rev. 00a 05/02/07 is61nlp102436/is61nvp102436 is61nlp204818/is61nvp204818 power supply characteristics (1) (over operating range) -200 -166 max max symbol parameter test conditions temp. range x18 x36 x18 x36 uni t i cc ac operating device selected, com. 450 450 400 400 ma supply current oe = v ih , zz v il , ind. 475 475 450 450 all inputs 0.2v or v dd ? 0.2v, typ. (2) 390 340 cycle time t kc min. i sb standby current device deselected, com. 210 210 175 175 ma ttl input v dd = max., ind. 220 220 185 185 all inputs v il or v ih , zz v il , f = max. i sbi standby current device deselected, com. 110 110 110 110 ma cmos input v dd = max., ind. 140 140 140 140 v in v ss + 0.2v or v dd ? 0.2v typ. (2) 75 75 f = 0 note: 1. mode pin has an internal pullup and should be tied to v dd or v ss . it exhibits 100a maximum leakage current when tied to v ss + 0.2v or v dd ? 0.2v. 2. typical values are measured at vcc = 3.3v, t a = 25 o c and not 100% tested. dc electrical characteristics (over operating range) 3.3v 2.5v symbol parameter test conditions min. max. min. max. unit v oh output high voltage i oh = ?4.0 ma (3.3v) 2.4 ? 2.0 ? v i oh = ?1.0 ma (2.5v) v ol output low voltage i ol = 8.0 ma (3.3v) ? 0.4 ? 0.4 v i ol = 1.0 ma (2.5v) v ih input high voltage 2.0 v dd + 0.3 1.7 v dd + 0.3 v v il input low voltage ?0.3 0.8 ?0.3 0.7 v i li input leakage current v ss v in v dd (1) ?5 5 ?5 5 a i lo output leakage current v ss v out v ddq , oe = v ih ?5 5 ?5 5 a
10 integrated silicon solution, inc. ? www.issi.com rev. 00a 05/02/07 is61nlp102436/is61nvp102436 is61nlp204818/is61nvp204818 3.3v i/o ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 1.5 ns input and output timing 1.5v and reference level output load see figures 1 and 2 317 5 pf including jig and scope 351 output +3.3v figure 1 figure 2 capacitance (1,2) symbol parameter cond itions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz, v dd = 3.3v. 3.3v i/o output load equivalent 1.5v output zo= 50 50
integrated silicon solution, inc. ? www.issi.com 11 rev. 00a 05/02/07 is61nlp102436/is61nvp102436 is61nlp204818/is61nvp204818 2.5v i/o ac test conditions parameter unit input pulse level 0v to 2.5v input rise and fall times 1.5 ns input and output timing 1.25v and reference level output load see figures 3 and 4 z o = 50 1.25v 50 output 1,667 5 pf including jig and scope 1,538 output +2.5v figure 3 figure 4 2.5v i/o output load equivalent
12 integrated silicon solution, inc. ? www.issi.com rev. 00a 05/02/07 is61nlp102436/is61nvp102436 is61nlp204818/is61nvp204818 read/write cycle switching characteristics (1) (over operating range) -200 -166 symbol parameter min. max. min. max. unit fmax clock frequency ? 200 ? 166 mhz t kc cycle time 5 ? 6 ? ns t kh clock high time 2 ? 2.5 ? ns t kl clock low time 2 ? 2.5 ? ns t kq clock access time ? 3.1 ? 3.5 ns t kqx (2) clock high to output invalid 1.5 ? 1.5 ? ns t kqlz (2,3) clock high to output low-z 1 ? 1 ? ns t kqhz (2,3) clock high to output high-z ? 3.0 ? 3.4 ns t oeq output enable to output valid ? 3.1 ? 3.5 ns t oelz (2,3) output enable to output low-z 0 ? 0 ? ns t oehz (2,3) output disable to output high-z ? 3.0 ? 3.4 ns t as address setup time 1.4 ? 1.5 ? ns t ws read/write setup time 1.4 ? 1.5 ? ns t ces chip enable setup time 1.4 ? 1.5 ? ns t se clock enable setup time 1.4 ? 1.5 ? ns t advs address advance setup time 1.4 ? 1.5 ? ns t ds data setup time 1.4 ? 1.5 ? ns t ah address hold time 0.4 ? 0.5 ? ns t he clock enable hold time 0.4 ? 0.5 ? ns t wh write hold time 0.4 ? 0.5 ? ns t ceh chip enable hold time 0.4 ? 0.5 ? ns t advh address advance hold time 0.4 ? 0.5 ? ns t dh data hold time 0.4 ? 0.5 ? ns t pds zz high to power down ? 2 ? 2 cyc t pus zz low to power down ? 2 ? 2 cyc notes: 1. configuration signal mode is static and must not change during normal operation. 2. guaranteed but not 100% tested. this parameter is periodically sampled. 3. tested with load in figure 2.
integrated silicon solution, inc. ? www.issi.com 13 rev. 00a 05/02/07 is61nlp102436/is61nvp102436 is61nlp204818/is61nvp204818 sleep mode timing sleep mode electrical characteristics symbol parameter cond itions min. max. unit i sb 2 current during sleep mode zz v ih 60 ma t pds zz active to input ignored 2 cycle t pus zz inactive to input sampled 2 cycle t zzi zz active to sleep current 2 cycle t rzzi zz inactive to exit sleep current 0 ns don't care deselect or read only deselect or read only t rzzi clk zz isupply all inputs (except zz) outputs (q) i sb2 zz setup cycle zz recovery cycle normal operation cycle t pds t pus t zzi high-z
14 integrated silicon solution, inc. ? www.issi.com rev. 00a 05/02/07 is61nlp102436/is61nvp102436 is61nlp204818/is61nvp204818 read cycle timing t kqx clk adv address write cke ce oe data out a1 a2 a3 t kh t kl t kc q3-3 q3-4 q3-2 q3-1 q2-4 q2-3 q2-2 q2-1 don't care undefined notes: write = l means we = l and bw x = l we = l and bw x = l ce = l means ce 1 = l, ce2 = h and ce 2 = l ce = h means ce 1 = h, or ce 1 = l and ce 2 = h, or ce 1 = l and ce2 = l t oehz t se t he t as t ah t ws t wh t ces t ceh t advs t advh t kqhz t kq t oeq t oehz q1-1
integrated silicon solution, inc. ? www.issi.com 15 rev. 00a 05/02/07 is61nlp102436/is61nvp102436 is61nlp204818/is61nvp204818 write cycle timing t ds t dh clk adv address write cke ce oe data in data out a1 a2 a3 t kh t kl t kc t se t he d3-3 d3-4 d3-2 d3-1 d2-4 d2-3 d2-2 d2-1 d1-1 don't care undefined notes: write = l means we = l and bw x = l we = l and bw x = l ce = l means ce 1 = l, ce2 = h and ce 2 = l ce = h means ce 1 = h, or ce 1 = l and ce 2 = h, or ce 1 = l and ce2 = l t oehz q0-3 q0-4
16 integrated silicon solution, inc. ? www.issi.com rev. 00a 05/02/07 is61nlp102436/is61nvp102436 is61nlp204818/is61nvp204818 single read/write cycle timing clk cke address write ce adv oe data out data in d5 t se t he t kh t kl t kc don't care undefined notes: write = l means we = l and bw x = l ce = l means ce 1 = l, ce2 = h and ce 2 = l ce = h means ce 1 = h, or ce 1 = l and ce 2 = h, or ce 1 = l and ce2 = l d2 t oelz t oeq a1 a2 a3 a4 a5 a6 a7 a8 a9 q1 q3 q4 q6 q7 t ds t dh
integrated silicon solution, inc. ? www.issi.com 17 rev. 00a 05/02/07 is61nlp102436/is61nvp102436 is61nlp204818/is61nvp204818 cke cke cke cke cke operation timing a1 a2 a3 a4 a5 a6 q1 q3 q4 clk cke address write ce adv oe data out data in d2 t se t he t kh t kl t kc t kqlz t kqhz t kq t dh t ds don't care undefined notes: write = l means we = l and bw x = l ce = l means ce 1 = l, ce2 = h and ce 2 = l ce = h means ce 1 = h, or ce 1 = l and ce 2 = h, or ce 1 = l and ce2 = l
18 integrated silicon solution, inc. ? www.issi.com rev. 00a 05/02/07 is61nlp102436/is61nvp102436 is61nlp204818/is61nvp204818 ce ce ce ce ce operation timing don't care undefined clk cke address write ce adv oe data out data in t se t he t kh t kl t kc notes: write = l means we = l and bw x = l ce = l means ce 1 = l, ce2 = h and ce 2 = l ce = h means ce 1 = h, or ce 1 = l and ce 2 = h, or ce 1 = l and ce2 = l d5 d3 t dh t ds t oelz t oeq q1 q2 q4 t kqhz t kqlz t kq a1 a2 a3 a4 a5
integrated silicon solution, inc. ? www.issi.com 19 rev. 00a 05/02/07 is61nlp102436/is61nvp102436 is61nlp204818/is61nvp204818 ordering information (3.3v core/2.5v- 3.3v i/o) commercial range: 0c to +70c configuration access time order part number package 1mx36 166 is61nlp102436-166tq 100 tqfp is61nlp102436-166tql 100 tqfp, lead-free is61nlp102436-166b3 165 pbga 2mx18 166 is61nlp204818-166tq 100 tqfp is61nlp204818-166tql 100 tqfp, lead-free is61nlp204818-166b3 165 pbga industrial range: -40c to +85c configuration access time order part number package 1mx36 166 is61nlp102436-166tqi 100 tqfp is61nlp102436-166tqli 100 tqfp, lead-free is61nlp102436-166b3i 165 pbga 2mx18 166 is61nlp204818-166tqi 100 tqfp is61nlp204818-166tqli 100 tqfp, lead-free is61nlp204818-166b3i 165 pbga
20 integrated silicon solution, inc. ? www.issi.com rev. 00a 05/02/07 is61nlp102436/is61nvp102436 is61nlp204818/is61nvp204818 ordering information (2.5v core/2.5v i/o) commercial range: 0c to +70c configuration access time order part number package 1mx36 166 is61nvp102436-166tq 100 tqfp is61nvp102436-166tql 100 tqfp, lead-free is61nvp102436-166b3 165 pbga 2mx18 166 is61nvp204818-166tq 100 tqfp is61nvp204818-166tql 100 tqfp, lead-free is61nvp204818-166b3 165 pbga industrial range: -40c to +85c configuration access time order part number package 1mx36 166 IS61NVP102436-166TQI 100 tqfp is61nvp102436-166tqli 100 tqfp, lead-free is61nvp102436-166b3i 165 pbga 2mx18 166 is61nvp204818-166tqi 100 tqfp is61nvp204818-166b3i 165 pbga
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. a 06/11/03 copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. packaging information a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 11 10 9 8 7 6 5 4 3 2 1 a1 corner bottom view d d1 e e e1 e 1 2 3 4 5 6 7 8 9 10 11 a1 corner top view a2 a a1 b (165x) ball grid array package code: b (165-pin) notes: 1. controlling dimensions are in millimeters. bga - 13mm x 15mm millimeters inches sym. min. nom. max. min. nom. max. n0. leads 165 165 a ? ? 1.20 ? ? 0.047 a1 0.25 0.33 0.40 0.010 0.013 0.016 a2 ? 0.79 ? ? 0.031 ? d 14.90 15.00 15.10 0.587 0.591 0.594 d1 13.90 14.00 14.10 0.547 0.551 0.555 e 12.90 13.00 13.10 0.508 0.512 0.516 e1 9.90 10.00 10.10 0.390 0.394 0.398 e? 1.00 ? ? 0.039 ? b 0.40 0.45 0.50 0.016 0.018 0.020
integrated silicon solution, inc. ? 1-800-379-4774 pk13197lq rev. d 05/08/03 packaging information tqfp (thin quad flat pack package) package code: tq thin quad flat pack (tq) millimeters inches millimeters inches symbol min max min max min max min max ref. std. no. leads (n) 100 128 a ? 1.60 ? 0.063 ? 1.60 ? 0.063 a1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 a2 1.35 1.45 0.053 0.057 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 0.17 0.27 0.007 0.011 d 21.90 22.10 0.862 0.870 21.80 22.20 0.858 0.874 d1 19.90 20.10 0.783 0.791 19.90 20.10 0.783 0.791 e 15.90 16.10 0.626 0.634 15.80 16.20 0.622 0.638 e1 13.90 14.10 0.547 0.555 13.90 14.10 0.547 0.555 e 0.65 bsc 0.026 bsc 0.50 bsc 0.020 bsc l 0.45 0.75 0.018 0.030 0.45 0.75 0.018 0.030 l1 1.00 ref. 0.039 ref. 1.00 ref. 0.039 ref. c0 o 7 o 0 o 7 o 0 o 7 o 0 o 7 o notes: 1. all dimensioning and tolerancing conforms to ansi y14.5m-1982. 2. dimensions d1 and e1 do not include mold protrusions. allowable protrusion is 0.25 mm per side. d1 and e1 do include mold mismatch and are determined at datum plane -h-. 3. controlling dimension: millimeters. d d1 e e1 1 n a2 a a1 e b seating plane c l1 l

▲Up To Search▲

Price & Availability of IS61NVP102436-166TQI

	To Download IS61NVP102436-166TQI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .